1. Field of the Invention
This invention relates to an organic electroluminescence display apparatus, a driving circuit for driving an organic electroluminescence light emitting portion and a driving method for an organic electroluminescence light emitting portion.
2. Description of the Related Art
In an organic electroluminescence display apparatus (hereinafter referred to as simply as organic EL display apparatus) which uses an electroluminescence device (hereinafter referred to merely as organic EL device) as a light emitting device, the luminance of the organic EL device is controlled by the value of electric current flowing through the organic EL device. Similarly as in a liquid crystal display apparatus, also in the organic EL display apparatus, a simple matrix method and an active matrix method are known as a driving method. The active matrix method has such various advantages that a high luminance image can be obtained although it has a drawback that the structure is complicated in comparison with the simple matrix method.
As a circuit for driving an organic electroluminescence light emitting portion (hereinafter referred to as light emitting portion) which is a component of the organic EL device, a driving circuit composed of five transistors and one capacitor element is known and disclosed, for example, in Japanese Patent Laid-Open No. 2006-215213. The driving circuit of the type just described is hereinafter referred to as 5Tr/1C driving circuit. The 5Tr/1C driving circuit is shown in FIG. 12. Referring to FIG. 12, the 5Tr/1C driving circuit includes five transistors including an image signal writing transistor TSig, a driving transistor TDrv, a light emission control transistor TEL—C, a first node initializing transistor TND1 and a second node initializing transistor TND2, and further includes a capacitor element C1. Here, a second one of the source/drain regions of the driving transistor TDrv forms a second node ND2, and the gate electrode of the driving transistor TDrv forms a first node ND1.
It is to be noted that the transistors and the capacitor element are hereinafter described in detail.
For example, each of the transistors is formed from an n-channel type thin film transistor (TFT), and a light emitting portion ELP is provided on an interlayer insulating layer or the like formed in such a manner as to cover the driving circuit. The anode electrode of the light emitting portion ELP is connected to the second one of the source/drain regions of the driving transistor TDrv. Meanwhile, a voltage VCat of, for example, 0 volt is applied to the cathode electrode of the light emitting portion ELP. Reference character CEL denotes parasitic capacitance of the light emitting portion ELP.
Referring to FIG. 13, the organic EL display apparatus includes
(1) a scanning circuit 101,
(2) an image signal outputting circuit 102,
(3) totaling N×M organic electroluminescence devices 10 arranged in a two-dimensional matrix wherein N organic EL devices 10 are arranged in a first direction and M organic EL devices 10 are arranged in a second direction different from the first direction, particularly in a direction perpendicular to the first direction, and each including an organic electroluminescence light emitting portion ELP and a driving circuit for driving the organic electroluminescence light emitting portion ELP,
(4) M scanning lines SCL connected to the scanning circuit 101 and extending in the first direction,
(5) N data lines DTL connected to the image signal outputting circuit 102 and extending in the second direction,
(6) a power supply section 100,
(7) a light emission controlling transistor control circuit 103,
(8) a first node initializing transistor control circuit 104, and
(9) a second node initializing transistor control circuit 105.
It is to be noted that, while, in FIG. 13, 3×3 organic EL devices 10 are shown for the convenience of illustration, this is merely illustrative.
A timing chart illustrating driving of the organic EL devices 10 is schematically illustrated in FIG. 14, and on/off states of the transistors are schematically illustrated in FIGS. 15A to 15D and 16A to 16E. Referring to FIG. 14, within a period TP(5)1, a pre-process for carrying out a threshold voltage cancellation process is executed. In particular, a first node initializing transistor control line AZND1 and a second node initializing transistor control line AZND2 are placed into the high level by operation of the first node initializing transistor control circuit 104 and the second node initializing transistor control circuit 105, respectively. Consequently, as seen in FIG. 15B, the first node initializing transistor TND1 and the second node initializing transistor TND2 are placed into an on state so that the potential at the first node ND1 is set to a voltage VOfs, for example, of 0 volt. On the other hand, the potential at the second node ND2 becomes equal to another voltage VSS, for example, of −10 volts. Consequently, the potential difference between the gate electrode and the second one of the source/drain regions of the driving transistor TDrv becomes greater than a threshold voltage Vth, for example, of 3 volts. The driving transistor TDrv remains in an on state.
Then, as seen in FIG. 14, within another period TP(5)2, a threshold voltage cancellation process is carried out. Before completion of the period TP(5)1, the second node initializing transistor control line AZND2 is placed into the low level to place the second node initializing transistor TND2 into an off state. Then, as seen in FIG. 15D, while the on state of the first node initializing transistor TND1 is maintained, a light emission controlling transistor control line CLEL—C is placed into the high level by operation of the light emission controlling transistor control circuit 103 at a starting timing of the period TP(5)2. Consequently, the light emission control transistor TEL—C is placed into an on state. As a result, the potential at the second node ND2 varies toward the potential of the difference of the threshold voltage Vth of the driving transistor TDrv from the potential at the first node ND1. In particular, the potential at the second node ND2 in a floating state rises. Then, when the potential difference between the gate electrode and the second one of the source/drain regions of the driving transistor TDrv reaches the threshold voltage Vth, then the driving transistor TDrv is placed into an off state. In this state, the potential at the second node ND2 is substantially equal to VOfs−Vth. Thereafter, within a period TP(5)3, while the on state of the first node initializing transistor TND1 is maintained, the light emission controlling transistor control line CLEL—C is placed into the low level by operation of the light emission controlling transistor control circuit 103 to place the light emission control transistor TEL—C into an off state. Then, within a period TP(5)4, the first node initializing transistor control line AZND1 is placed into the low level by operation of the first node initializing transistor control circuit 104 to place the first node initializing transistor TND1 into an off state.
Then, as seen in FIG. 14, within a period TP(5)5, a writing process into the driving transistor TDrv is carried out. In particular, as seen in FIG. 16C, while the off state of the first node initializing transistor TND1, second node initializing transistor TND2 and light emission control transistor TEL—C is maintained, the potential at a data line DTL is set to a voltage corresponding to an image signal, that is, an image signal (driving signal or luminance signal) VSig for controlling the luminance of the light emitting portion ELP. Then, a scanning line SCL is placed into the high level to place the image signal writing transistor TSig into an on state. As a result, the potential at the first node ND1 rises to the image signal VSig. Charge based on the variation of the potential at the first node ND1 is distributed to the capacitor element C1, parasitic capacitance CEL of the light emitting portion ELP, and parasitic capacitance between the gate electrode of the driving transistor TDrv and that one of the source/drain regions of the driving transistor TDrv which is adjacent the light emitting portion ELP. Accordingly, if the potential at the first node ND1 varies, then the potential also at the second node ND2 varies. However, as the capacitance value of the parasitic capacitance CEL of the light emitting portion ELP increases, the variation of the potential at the second node ND2 decreases. Then, generally the capacitance value of the parasitic capacitance CEL of the light emitting portion ELP is higher than the capacitance value of the capacitor element C1 and the value of the parasitic capacitance of the driving transistor TDrv. Therefore, if it is assumed that the potential at the second node ND2 little varies, then the potential difference Vgs between the gate electrode and the second one of the source/drain regions of the driving transistor TDrv has a value defined by the following expression (A):Vgs≈VSig−(VOfs−Vth)  (A)
Thereafter, as seen in FIG. 14, within a period TP(5)6, a mobility correction process of raising the potential at the second one of the source/drain regions of the driving transistor TDrv, that is, the potential at the second node ND2, in response to a characteristic of the driving transistor TDrv, for example, in response to the magnitude of the mobility μ. In particular, as seen in FIG. 16D, while the on state of the driving transistor TDrv is maintained, the light emission control transistor TEL—C is placed into an on state by operation of the light emission controlling transistor control circuit 103, and then, after predetermined time t0 passes, the image signal writing transistor TSig is placed into an off state. As a result, where the value of the mobility μ of the driving transistor TDrv is high, the rise amount ΔV, that is, the potential correction amount, of the potential in the second one of the source/drain regions of the driving transistor TDrv, is great, but where the value of the mobility μ of the driving transistor TDrv is low, the rise amount ΔV, that is, the potential correction amount, of the potential at the second one of the source/drain regions of the driving transistor TDrv, is small. Here, the potential difference Vgs between the gate electrode and the second one of the source/drain regions of the driving transistor TDrv is transformed from the expression (A) into an expression (B) given below. It is to be noted that the overall time t0 of the predetermined time, that is, the period TP(5)6, for executing the mobility correction process may be determined in advance as a design value upon designing of the organic EL display apparatus.Vgs≈VSig−(VOfs−Vth)−ΔV  (B)
By the operation described above, the threshold value cancellation process, writing process and mobility correction process are completed. Then, within a later period TP(5)7, the image signal writing transistor TSig is placed into an off state, and the first node ND1, that is, as seen in FIG. 16E, the gate electrode of the driving transistor TDrv is placed into floating state. On the other hand, the light emission control transistor TEL—C maintains the on state, and the first one of the source/drain regions of the light emission control transistor TEL—C remains connected to a power supply section of a voltage VCC, for example, of 20 volts for controlling light emission of the light emitting portion ELP. Accordingly, as a result of the foregoing, the potential at the second node ND2 rises, and a phenomenon similar to that which occurs with a bootstrap circuit occurs with the gate electrode of the driving transistor TDrv and also the potential at the first node ND1 rises. As a result, the potential difference Vgs between the gate electrode and the second one of the source/drain regions of the driving transistor TDrv maintains the value of the expression (B). Further, since current flowing through the light emitting portion ELP is drain current Ids which flows from the drain region to the source region of the driving transistor TDrv, if the driving transistor TDrv operates ideally in the saturation region, then the drain current Ids can be represented by the expression (C). The light emitting portion ELP emits light with luminance corresponding to the value of the drain current Ids.
                                                                        I                ds                            =                            ⁢                              k                ·                μ                ·                                                      (                                                                  V                        gs                                            -                                              V                        th                                                              )                                    2                                                                                                        =                            ⁢                              k                ·                μ                ·                                                      (                                                                  V                        Sig                                            -                                              V                        Ofs                                            -                                              Δ                        ⁢                                                                                                  ⁢                        V                                                              )                                    2                                                                                        (        C        )            